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.intel_syntax noprefix
.section .text
.global halt
halt:
1: hlt
jmp 1b
.global set_gdt
set_gdt:
lgdt [rdi]
push rsi
lea rax, 1f
push rax
retfq
1: mov ds, rdx
mov es, rdx
mov fs, rdx
mov gs, rdx
mov ss, rdx
ltr rcx
ret
.global set_idt
set_idt:
lidt [rdi]
ret
.global disable_interrupts
disable_interrupts:
cli
ret
.global enable_interrupts
enable_interrupts:
sti
ret
#define DEFINE_ISRS \
ISR(0) \
ISR(1) \
ISR(2) \
ISR(3) \
ISR(4) \
ISR(5) \
ISR(6) \
ISR(7) \
ISR(8) \
ISR(9) \
ISR(10) \
ISR(11) \
ISR(12) \
ISR(13) \
ISR(14) \
ISR(15) \
ISR(16) \
ISR(17) \
ISR(18) \
ISR(19) \
ISR(20) \
ISR(21) \
ISR(22) \
ISR(23) \
ISR(24) \
ISR(25) \
ISR(26) \
ISR(27) \
ISR(28) \
ISR(29) \
ISR(30) \
ISR(31)
.extern interrupt_handler
#define ISR(n) \
isr_stub_##n: \
mov rdi, n; \
call interrupt_handler; \
iretq;
DEFINE_ISRS
#undef ISR
#define ISR(n) \
.quad isr_stub_##n;
.section .data
.global isr_stubs
isr_stubs:
DEFINE_ISRS
#undef ISR
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